In a conventional process flow for a nanowire-based field effect transistor (FET), a nanowire (the FET channel) is formed by patterning a silicon-on-insulator (SOI) layer (or a silicon-on-silicon germanium (SiGe) film). The nanowire is suspended by etching the buried oxide (BOX) under the SOI layer (or etching the SiGe film). Suspension of the nanowire is needed so that a gate conductor can be placed under the nanowire (in addition to on the sidewalls and top surfaces thereof). Such a gate configuration is also commonly referred to as a “wrapped-around” gate, since the gate wraps around the circumference of the nanowire channel. The definition of a wrapped-around gate by reactive ion etching (RIE) is challenging since some amount of isotropic etching is needed to clear the gate material shadowed by the suspended nanowire (the gate material that is beneath the nanowire in regions which are not part of the gated channel region). While an isotropic sideways etch is effective at removing the gate material beneath the nanowire, this process also attacks the rest of the gate line. This effect is particularly problematic when the gate line dimensions are comparable to the amount of shadowed gate material that is targeted by the isotropic etch. The isotropic etch can substantially trim the gate line, which leads to a poor control over the gate line dimensions.
Therefore, improved techniques for fabricating nanowire-based MOSFETs with a wrapped-around gate would be desirable.